Project 01-05SysTest

SYSTEST - Developing Methodology for Advanced System Testing


Summary

This European project is developing, documenting and evaluating methodology that can improve the time-to-market, cost, and risk of system development by improving the verification and validation.

This project is partially funded by the European Commission Fifth Framework Programme


Background

The primary challenge in commercial systems is to reduce time-to-market and cost while customizing high-quality products. As an example, the lead time to design and produce a car has dropped from 5-6 years (1980s) to less than 2 years. At the same time, consumers demand higher quality at lower purchase price. Therefore, controlling schedule, costs and quality remains a major challenge for modern agile factories.

Increasing complexity, decreasing budgets, and shorter time-to-market cause industry to search for new methods to improve the overall process. Testing continues to consume as much as 40% of new product development. Therefore, a critical link is Systems Verification Validation & Testing (VVT).

VVT focuses on ensuring that systems are delivered functionally sound, meeting or exceeding the users’ needs, with an acceptable level of risk. Most industries perform VVT during a very late and narrow phase of the product life cycle. As a result the overall development time and cost associated with product rework frequently exceeds 20%.

The goals of the SYSTEST project are:

  • Decrease product development costs and time to market by 10% by halving the cost of product rework.
  • Improve by 10% the following system qualities: correctness, robustness and performance.
  • Ensure prudent and rational utilisation of natural resources by providing early indicators of flaws in product development.

Approach

The SYSTEST project is improving the VVT processes by:

  • Gathering the generic VVT body of knowledge from a variety of product domains, capturing that knowledge in documented methodology and in a useable software model.
  • Adapting the generic knowledge based on industry and project-specific knowledge
  • Assessing the worth of the methods by measuring their use on real pilot projects.

SYSTEST products are:

  • VVT Methodology Guidelines (VVTMG) - a document containing the gathered body of knowledge in a project-useable form.
  • VVT Process Model (VVTPM) - a software tool to evaluate strategies for VVT implementation in terms of their impact on project time-to-market, cost, and risk.
  • Methodology Assessment - a research basis of information demonstrating the improved performance of the VVTMG and VVTPM against previous methods, based on the pilot projects.
  • Exploitation - the participating companies start using these effective methods as part of the pilot projects, and in other projects.
  • Dissemination - publications throughout industry that provide the products to others for use in their projects, or to foster further research.


Participants

SYSTEST participants are:

  • Israel Aircraft Industries Ltd - aircraft design and manufacture (Project Coordinator)
  • Daimler Chrysler AG - automotive design and manufacture
  • Tetrapak Packaging Systems SpA - automated packaging systems design and manufacture
  • Centro Richerche Fiat - automotive research and development
  • Ąceralia Corporacion Siderurgica - metallurgical systems development
  • Technische Universitaet Muenchen - academic research center
  • Norwegian Systems Engineering Council (NORSEC) - an INCOSE chapter and SECOE participants

Funding

Funding is provided under the European Commission (EC) Competitive and Sustainable Growth Fifth Framework Programme. Partial funding is provided by EC, with the corporate participants providing the remainder. Total project funding over 36 months is in excess of 4 million Euros.


Contact Information

For more information about the SysTest project or to obtain the VVT Methodology Guidelines, contact Avner Engel of Israel Aircraft Industries at aengel@iai.co.il


Page last modified 23 Sep 04

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